RISC-V /Debug /Trigger Extra (RV64) (textra64)

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Interpret as Trigger Extra (RV64) (textra64)

63 6059 5655 5251 4847 4443 4039 3635 3231 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0sselect 0svalue0sbytemask 0mhselect 0mhvalue

Description

This register provides access to the trigger selected by {csr-tselect}. The reset values listed here apply to every underlying trigger.

This register is accessible as {csr-tdata3} when {tdata1-type} is 2, 3, 4, 5, or 6 and XLEN=64. The function of the fields are defined above, in {csr-textra32}. This register retains its value when XLEN changes. When XLEN=32 some of the bits can be accessed through {csr-textra32}.

Byte-granular comparison of {csr-scontext} to {textra64-svalue} in {csr-textra64} allows {csr-scontext} to be defined to include more than one element of comparison. For example, software instrumentation can program the {csr-scontext} value to be the concatenation of different ID contexts such as process ID and thread ID. The user can then program byte compares based on {textra64-sbytemask} to include one or more of the contexts in the compare.

Byte masking only applies to {csr-scontext} comparison; i.e when {textra64-sselect} is 1.

Fields

sselect
svalue
sbytemask

When the least significant bit of this field is 1, it causes bits 7:0 in the comparison to be ignored, when {textra64-sselect}=1. Likewise, the second bit controls the comparison of bits 15:8, third bit controls the comparison of bits 23:16, and fourth bit controls the comparison of bits 31:24.

mhselect
mhvalue

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